数字系统设计:Verilog ＆ VHDL版:英文版_PDF下载[114MB-百度云](美)EnochO.Hwang著

本书特色

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随着微电子技术与计算机技术的飞速发展，以及先进的电子设计自动化（EDA）技术及现场可编程门阵列（FPGA）器件的广泛应用，现代数字逻辑电路与系统的设计理念及实现技术已经发生了翻天覆地的变化。本书以微处理器系统作为复杂数字逻辑系统的代表，在简要介绍其工作原理的基础上，以CPU硬件结构框图为线索贯穿各个章节，详细讲述了如何构建基本组合/时序逻辑元件、如何利用已有元件组建数据通路与控制单元部件、如何利用已有部件实现一个通用CPU，以及如何通过进一步添加简单的输入输出接口来*终搭建出一个完整的微处理器系统。本书通过在简单的数字逻辑元件与复杂的实用数字逻辑系统之间搭建桥梁，能够帮助读者深刻理解数字逻辑组件的设计与使用方法，进而全面和清晰地把握复杂数字系统的EDA设计与实现技术要点。本书及相关网站提供了丰富的实用学习资源，所有设计示例都提供了电路图以及Verilog与VHDL源码。

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内容简介

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本书通过在简单的数字逻辑元件与复杂的实用数字逻辑系统之间搭建桥梁，能够帮助读者深刻理解数字逻辑组件的设计与使用方法，进而全面和清晰地把握复杂数字系统的EDA设计与实现技术要点。本书及相关网站提供了丰富的实用学习资源，所有设计示例都提供了电路图以及Verilog与VHDL源码。

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作者简介

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Enoch O. Hwang 于美国加州大学Riverside分校获计算机科学博士学位，目前是南加州Sierra大学计算机科学系助理教授，加州大学Riverside分校电子工程系、计算机科学与工程系讲师，主要讲授数字逻辑设计课程。
Enoch O. Hwang 于美国加州大学Riverside分校获计算机科学博士学位，目前是南加州Sierra大学计算机科学系助理教授，加州大学Riverside分校电子工程系、计算机科学与工程系讲师，主要讲授数字逻辑设计课程。

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Chapter 1　Introduction to Microprocessor Design1.1　Overview of Microprocessor Design 1.2　Design Abstraction Levels1.3　Examples of a 2-to-1 Multiplexer1.3.1　Behavioral Level 1.3.2　Gate Level 1.3.3　Transistor Level 1.4　Introduction to Hardware Description Language1.5　Synthesis1.6　Going Forward1.7　ProblemsChapter 2　Fundamentals of Digital Circuits2.1　Binary Numbers 2.1.1　Counting in Binary2.1.2　Converting between Binary and Decimal2.1.3　Octal and Hexadecimal Notations 2.1.4　Binary Number Arithmetic 2.2　Negative Numbers 2.2.1　Two’s Complement Representation2.2.2　Sign Extension 2.2.3　Signed Number Arithmetic 2.3　Binary Switch2.4　Basic Logic Operators and Logic Expressions 2.5　Logic Gates2.6　Truth Tables2.7　Boolean Algebra and Boolean Equations2.7.1　Boolean Algebra2.7.2　Duality Principle2.7.3　Boolean Functions and Their Inverses 2.8　Minterms and Maxterms2.8.1　Minterms 2.8.2　Maxterms 2.9　Canonical, Standard, and Non-Standard Forms2.10　Digital Circuits2.11　Designing a Car Security System2.12　Verilog and VHDL Code for Digital Circuits 2.12.1　Verilog Code for a Boolean Function 2.12.2　VHDL Code for a Boolean Function2.13　ProblemsChapter 3　Combinational Circuits 653.1　Analysis of Combinational Circuits 3.1.1　Using a Truth Table 3.1.2　Using a Boolean Function3.2　Synthesis of Combinational Circuits 3.2.1　Using Only NAND Gates3.3　Minimization of Combinational Circuits 3.3.1　Boolean Algebra 3.3.2　Karnaugh Maps3.3.3　Don’t-Cares 3.3.4　Tabulation Method3.4　Timing Hazards and Glitches3.4.1　Using Glitches 3.5　BCD to 7-Segment Decoder3.6　Verilog and VHDL Code for Combinational Circuits3.6.1　Structural Verilog Code 3.6.2　Structural VHDL Code3.6.3　Dataflow Verilog Code 3.6.4　Dataflow VHDL Code3.6.5　Behavioral Verilog Code3.6.6　Behavioral VHDL Code3.7　Problems Chapter 4　Standard Combinational Components4.1　Signal Naming Conventions4.2　Multiplexer4.3　Adder 4.3.1　Full Adder4.3.2　Ripple-Carry Adder4.3.3　Carry-Lookahead Adder4.4　Subtractor 4.5　Adder-Subtractor Combination4.6　Arithmetic Logic Unit4.7　Decoder4.8　Tri-State Buffer4.9　Comparator 4.10　Shifter4.11　Multiplier4.12　Problems Chapter 5 Sequential Circuits5.1　Bistable Element5.2　SR Latch5.3　Car Security System—Version 25.4　SR Latch with Enable5.5　D Latch5.6　D Latch with Enable5.7　Verilog and VHDL Code for Memory Elements5.7.1　VHDL Code for a D Latch with Enable5.7.2　Verilog Code for a D Latch with Enable5.8　Clock5.9　D Flip-Flop5.9.1　Alternative Smaller Circuit5.10　D Flip-Flop with Enable5.10.1　Asynchronous Inputs5.11　Description of a Flip-Flop5.11.1　Characteristic Table5.11.2　Characteristic Equation5.11.3　State Diagram5.12　Register5.13　Register File5.14　Memories5.14.1　ROM5.14.2　RAM5.15　Shift Registers5.15.1　Serial-to-Parallel Shift Register5.15.2　Serial-to-Parallel and Parallel-to-Serial Shift Register5.15.3　Linear Feedback Shift Register5.16　Counters5.16.1　Binary Up Counter5.16.2　Binary Up Counter with Parallel Load5.17　Timing Issues5.18　ProblemsChapter 6　Finite-State Machines6.1　Finite-State Machine Models6.2　State Diagrams6.3　Analysis of Finite-State Machines6.3.1　Next-State Equations6.3.2　Next-State Table6.3.3　Output Equations6.3.4　Output Table6.3.5　State Diagram6.3.6　Example6.4　Synthesis of Finite-State Machines6.4.1　State Diagram6.4.2　Next-State Table6.4.3　Next-State Equations6.4.4　Output Table and Output Equations6.4.5　FSM Circuit6.5　Optimizations for FSMs6.5.1　State Reduction6.5.2　State Encoding6.5.3　Unused States6.6　FSM Construction Examples6.6.1　Car Security System—Version 36.6.2　Modulo-6 Up-Counter6.6.3　One-Shot Circuit6.6.4　Simple Microprocessor Control Unit6.6.5　Elevator Controller Using a Moore FSM 6.6.6　Elevator Controller Using a Mealy FSM6.7　Verilog and VHDL Code for FSM Circuits6.7.1　Behavioral Verilog Code for a Moore FSM6.7.2　Behavioral Verilog Code for a Mealy FSM6.7.3　Behavioral VHDL Code for a Moore FSM6.7.4　Behavioral VHDL Code for a Mealy FSM6.8　Problems Chapter 7　Dedicated Microprocessors7.1　Need for a Datapath7.2　Constructing the Datapath 7.2.1　Selecting Registers 7.2.2　Selecting Functional Units7.2.3　Data Transfer Methods7.2.4　Generating Status Signals7.3　Constructing the Control Unit7.3.1　Deriving the Control Signals7.3.2　Deriving the State Diagram 7.3.3　Timing Issues7.3.4　Deriving the FSM Circuit7.4　Constructing the Complete Microprocessor7.5　Dedicated Microprocessor Construction Examples7.5.1　Greatest Common Divisor 7.5.2　High-Low Number Guessing Game7.5.3　Traffic Light Controller7.6　Verilog and VHDL Code for Dedicated Microprocessors7.6.1　FSM1D Model7.6.2　FSMD Model7.6.3　Algorithmic Model7.7　ProblemsChapter 8　General-Purpose Microprocessors8.1　Overview of the CPU Design8.2　The EC-1 General-Purpose Microprocessor8.2.1　Instruction Set8.2.2　Datapath8.2.3　Control Unit8.2.4　Complete Circuit8.2.5　Sample Program8.2.6　Simulation8.2.7　Hardware Implementation 8.3　The EC-2 General-Purpose Microprocessor8.3.1　Instruction Set 8.3.2　Datapath8.3.3　Control Unit 8.3.4　Complete Circuit8.3.5　Sample Program8.3.6　Hardware Implementation8.4　Extending the EC-2 Instruction SetChapter 9　Interfacing Microprocessors9.1　Multiplexing 7-Segment LED Display 9.1.1　Theory of Operation9.1.2　Controller Design9.2　Issues with Interfacing Switches9.3　3×4 Keypad Controller9.3.1　Theory of Operation9.3.2　Controller Design